The FPGA market is difficult crack since the industry leaders, Altera and Xilinx, have well-entrenched positions -- making it particularly difficult for startups to make headway.  A new FPGA company, Tabula, recently emerged from stealth mode to take on the FPGA giants with a new architecture dubbed "Spacetime."  The company even took cues from Albert Einstein's space-time cones to construct its logo with the orange cones.   In its coming out road show, the company unveiled its ABAX family of 40nm-based 3PLDs.

The company's name, "Tabula" is derived from the Latin Tabula Rasa which means "blank slate."  The company's devices are, in effect, turning "blank slates" into configured silicon chip designs.  The product family moniker "Abax" has its roots in the word "abacus" used by the ancient Greeks and Chinese for calculation.

Tabula was founded in December 2003 by Steve Teig and Michal Jacobi.  Teig, who serves at the startup as president and chief technology officer, was formerly a CTO at Cadence Design Systems.  This is his fifth venture.   He has two biotech (CombiClean and BioCAD) and two EDA (Trilogy Systems and Tangent Systems) startups under his belt.  The most recent was Simplex Solutions which went public and was acquired by Cadence.  Jacobi, VP of business operations, was responsible for the U.S. operations of two early stage software companies.  Teig and Jacobi had worked together at BioCAD and Tangent Systems (acquired by Cadence).

Dennis Segers (Top), Steve Teig (Bottom)

Dennis Segers, CEO, joined Tabula in May 2006.  Prior to Tabula he served as president, CEO, and director of Matrix Semiconductor. Matrix pioneered the design and development of three-dimensional integrated. At Matrix, Dennis oversaw the transition of the company from the early technology feasibility phase to high volume production, culminating in the acquisition of the company by SanDisk in January 2006.  Previously, he served as the senior VP and GM of the FPGA product groups at Xilinx. He oversaw the development and introduction of the Virtex family FPGAs, the most successful programmable logic family in the industry's history -- growing the division from a $300 million business to over $1.4 billion.

Others on the management team include:

• Alain Bismuth, VP of marketing (ex-Alter, LSI Logic, IBM)
• Steven Haynes, VP of sales (ex-Xilinx)
• Matt Crowley, VP of hardware development (ex-Sandisk, Matrix Semiconductor, AMD, NexGen, Amdahl)
• Daniel Gitlin, VP of manufacturing technology (ex-Xilinx, LSI Logic)
• Rajeev Jayaraman, VP of software development (ex-Xilinx)
• Mike Staiger, CFO (ex-Copper Mountain Networks)

Tabula is well funded with first tier VCs and has built the company to 110 employees -- almost all working out of the headquarters office in Santa Clara, Calif.  In February 2009, the company received a $24 million second tranche of its Series C equity financing, bringing the total amount of Series C funding to $74 million. The additional funding came from Tabula's existing investors Greylock Partners, Benchmark Capital, NEA, Crosslink Capital, DAG Ventures, Balderton Capital, Integral Capital Partners, and SVB Capital.  To date, Tabula received a total of $106 million in outside investment.  This large amount of funding attests to the difficulty in bringing to market novel reprogrammable technologies.  Since both Altera and Xilinx are believe to be migrating to the 28 nanometer node later this year, they will keep the pressure on Tabula.  As a result Tabula will need more funding in the future, in our view.

What is Spacetime?  A virtual 3-D fabric?   A typical LUT, the essence of FPGAs, is reprogrammed/cycled eight times with entirely different logic configurations with a very speedy 1.6GHz spacetime clock and controller.  The virtually created eight LUT configurations are completed in one user clock cycle (typically 800MHz clock) -- thus a theoretical eight-fold increase in density.  The complexity of the architecture is masked by Tabula's proprietary place-and-route EDA tool.  That is a good thing, since engineers loathe having to learn new design methodologies.  The design flow follows conventional FPGA flows except for the proprietary synthesis and place-and-route.

A Spacetime architecture white paper is available for download.

A home-grown Tabula short movie explains the concepts.

 
Tabula's ABAX product launch consists of four chips offering between 220K and 630K virtual 4-input LUTs and fine-tuned to the needs of the communications markets.   All family members feature 5.5M-bytes of RAM, and use the same 1936-pin BGA package with 920 parallel I/O pins and 48 high speed I/O pins which support a variety of SerDes standards.  The design flow is similar to FPGA and ASIC flows using synthesis, placement, and routing to compile designs from RTL into silicon automatically. To increase designers' productivity, ABAX also supports a broad portfolio of soft IP cores. ABAX products are manufactured using TSMC's 40 nanometer process.

Advantages claimed by the Spacetime architecture compared to FPGAs:

1. 2.5x logic density
2. 2x memory density
3. 2.9x memory ports
4. 3.7 x DSP performance

Tabula spent its first four years developing the architecture.  Since 2007, the company began taping out silicon test chips.  The company said it has validated that Spacetime works and by late 2008 the first parts coming out of developing were being tested.  Tabula has placed early developmental samples in the hands of a few customers, broader production and sampling expected in Q3 2010.  The first device to be rolled out is the A1EC04.  The others in the family will be introduced in the second half of 2010.  The pricing for family is expected to be range between $105 to $200 for several thousand unit quantities -- compared to currently high-end FPGAs going for $1,000+ in volume. 

Initially, Tabula decided to target communications customers which include network infrastructure, wireless and telecom segments.  The company believe that these customers create the best value proposition as the technology is brought to market.  While the company has not announced any reference customers, the market is populated by tier one companies, such as Cisco, Siemens, Motorola, Samsung, Ericsson, Juniper, Alcatel-Lucent and Huawei.  Tabula believes that these market segments represent a $1.4 billion opportunity today and is expected to grow to $2 billion+ over the next four years.

The FPGA industry has seen its startup challengers come and go in an attempt to challenge Altera and Xilinx with new techniques.  A dozen or so of these new ventures failed due to strategic marketing issues, incremental feature benefits, or developments system limitations (Ambric, Leopard Logic, Mathstar, Velogix, Cswitch, others).  Two other public companies, Actel and Lattice Semiconductor, remain as the only significant alternatives.  Estimated market shares of current FPGA suppliers, $3.7 billion market in 2009:

While the Spacetime technology is the first commercialization of this reconfigurability approach, Xilinx worked on similar projects and could not get it to work.  Presumably, they hold patents reconfigurable FGPA technologies.  Tabula itself claims 150 patents filed or granted.

Tabula's technique to rapidly reconfigure the array using time has some novel twists which the startup claims to enable smaller dies sizes, 2.5x logic densities, thus lowering costs.   The technology is intended to take market share from Xilinx and Altera's 40nm-based devices.  Most importantly, if Tabula can hit its price points of $100-200 for the family profitably, range of applications will expand.  

Other FPGA-related startups are clamoring to break out of the pack:

• SiliconBlue focused on low power
• Achronix aiming for extremely high-performance
• Abound Logic shooting for designing the largest FPGAs
• Tier Logic using 3-D stacked layers

Even with the spotty history of reconfigurable SoC startups, Tabula cannot be dismissed.  It has one of the best management teams we have seen in a startup in the past few years.   Aside from being founded by EDA veteran, Teig and led by Dennis Seegers, the "Father of Virtex" at Xilinx, the team has good number of star employees from Xilinx, Altera, Cadence, Simplex and Matrix Memory.

Since communications markets require a longer design-in and approval cycle (2-3 years), the jury is out on the company for now.  Neither Altera nor Xilinx will feel the heat from Tabula in the short term.  If Tabula can execute its product rollout as planned, the leaders will have to take note as the price differential is too large between current offerings and what would be available with ABAX devices.

Contact:
Tabula
3250 Olcott St.
Santa Clara, CA 95054
Web: www.tabula.com
Tel: (408) 986-9140
Fax: (408) 986-9146