Tilera was founded in October 2004 following extensive basic development work done on mesh network processors at Massachusetts Institute of Technology.  The startup's name, 'Tilera,' is based on the word combination of "Tile Era" which hints of the company's "Tile Processor Architecture."

The origins of the company date back to 1996 when academics at MIT were contemplating the future issues of designing very large and complex digital chips.  Their novel ideas were first espoused in 1997 in a paper published in IEEE Computer, which dealt with the "billion transistor" issue and what the resulting IC architecture might look like.  The concept of tiled multicore architecture took hold. During the next 10 years with multi-million grant funding from DARPA and NSF, the MIT team worked on bringing the technology to life.  In 2002, the researchers were able to demonstrate the first multicore chips dubbed as the "RAW" multicore processor.  This test unit had 16 cores operating at 425MHz clock and 6.8 BOBS.  The chip was fabricated in 0.18-micron technology using an IBM SA27E standard cell.

Why are startups delving into the multicore technology?  From the silicon/IP provider's perspective, evolution to multicore architectures represents an alternative approach to increased performance per watt compared to the continuous ratcheting up of the clock speeds of single processors.  Heat dissipation, power consumption, and packaging limitations are particularly important factors.

Tilera's long gestation period was followed with Series A funding totaling a respectable $16 million.  Initial investors who believed in the new concept were Bessemer Venture Partners and Walden International.  In February of 2007, the company attracted its second sizable funding round from the initial investors and new VCs Columbia Capital and TSMC's venture arm, VTA (VentureTech Alliance).  The total raised in the B round was about $24 million.

Tilera's evolution is highlighted in the chart below.

Anant Agarwal, the principal founder and chief technology officer, took a two-year leave of absence from MIT and with his initial team of MIT technologists and industry personnel formed Tilera in stealth mode.  He is a professor of Electrical Engineering and Computer Science at MIT, and a member of the CSAIL Laboratory.  Agarwal has been a founder of several other start-ups, including Virtual Machine Works (1993).  Now part of Mentor Graphics, VMW solved logic emulation by combining 100's of FPGA's using a mesh interconnect and a patented 'virtual wires' compiler.  While a professor at Stanford in the early 1980s, he worked on the design of the MIPS chips, which put Silicon Graphics on the technology map.

Agarwal defined the "kill rule" for multicore.  It states that a resource in a core must be increased in area only if the core's performance improvement is at least proportional to the core's area increase.  Put another way, increase resource size only if for every 1% increase in core area there is at least a 1% increase in core performance.

The company's top management team is shown in the chart below.

Devesh Garg is a co-founder, president, and CEO and additionally serves as an operating partner at Bessemer Venture Partners. Prior to joining Bessemer in 2003, he spent five years at Broadcom, having joined the company as an original member. As the GM of Broadcom's Security Business Unit, Garg was responsible for the overall security strategy, including the architecture, design, development, and marketing of SSL and IPSEC co-processors, security systems and software. While at Broadcom, he also held executive management responsibilities for technical sales and field application engineering for all of Broadcom's products.

John Brown, a co-founder, joined Tilera in May 2005 and serves as VP of IC Engineering.  Previously, as an AMD Fellow, he led an architecture team targeting the Athlon 64 (for desktop), Turion (for mobile), and Sempron (value mobile/desktop). Prior to that, Brown was director of logic and architecture at C-Port , producing the C5 Network Processor. C-Port was acquired by Motorola in 2000. From 1980-1998 Brown worked at Digital Semiconductor where he contributed to the VAX 8200, VAX 6400, VAX 6600, Alpha 21066, and Alpha 21264 microprocessor designs and architecture.

Richard Schooler, VP of software engineering, came to Tilera from Microsoft where he was director of Windows Build.  He has served as a technical director at VERITAS Software, VP of technology at Geodesic Systems, the CTO for InCert Software, and worked in project management and software engineering roles at Hewlett Packard, Bolt Beranek & Newman Advanced Computers, and Intermetrics.

Nagaraj Murthy, VP of operations,  was previously VP of operations at Greenfield Networks which was acquired by Cisco.  He served in senior operational and engineering roles at Silicon Access, ATI, and Sun, and has been responsible for bringing to market complex ASICs, microprocessors, graphics engines and network processors.

Rao Gattupalli came to Tilera in December 2006 to assume the role of VP of applicatons. Previously, as the director of engineering for L4-L7 services in the Security Technology Group (STG) at Cisco Systems, he was responsible for the Content Switching Module (CSM) and the led the development effort on the industry leading 16Gbps Application Control Engine (ACE).  Prior to that, Gattupalli was director of HW at Netiverse, which was acquired by Cisco in 2000.  He was also the director of HW development at Tharas Systems, a provider of the industry leading Verilog Accelerator.  In addition, he held several management positions at SGI and worked at Intel, Catalyst Semiconductor, and Nexcom Technology (acquired by ISSI). 

Vijay Aggarwal,VP of business development, joined Tilera in October 2004.  He was the CTO and founder of Gotham Networks where he was responsible for architecture and design of a network processor.  Previously Aggarwal was a system architect at Nexabit Networks where he was responsible for first round of terabit router architectures and system design.  Nexabit was sold to Lucent Technologies.

Bob Doud, director of marketing, has previously worked at a number of networking silicon companies including Hifn, NetOctave and SafeNet in roles ranging from senior system architect to product line director.  He also spent a number of years in the security appliance industry in both engineering and technologist roles

Tilera participates in the embedded intelligent networking and digital video markets where there are huge demands for high performance and power efficiency.  The intelligent networking space is now seeing 10x to 100x increase in computing performance requirements due to expanded value-added service offerings within the network.  In video teleconferencing, for example, manufacturers are moving to high-definition and to better compression schemes using H.264 versus the older MPEG2 technology.  This creates 10x to 20x increases in computing demand.

The company's technology aims to circumvent several key challenges in deploying multicore chip designs which by 2014 may require upwards of 1,000 cores in a complex chip.  These are:

• Limited or no scalability beyond 4 to 8 cores
• Inefficient power operation
• Lack of suitable programming to implement the solution

Tilera blames the currently popular bus structure implementation as the main culprit in preventing efficient scalability beyond eight cores in multicore processors where every packed has to go through a central switch creating a critical bottleneck.  To overcome this limitation, Tilera's approach was to develop a mesh-enabled tile architecture in which each tile building block consisting of a processing core plus a switch.

Tilera's technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates an efficient 2-dimensional traffic system for packets, much like the layout of a modern city's streets. Tilera's implementation of this grid architecture is called iMesh^TM  (intelligent Mesh).  Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a "computing-by-the-yard" scalability.

Tilera's flagship product is its recently introduced TILE64^TM multicore processor, which touts 500 BOPS, 600MHz-900MHz clock speed, and 170-300mW power per tile.  In order to minimize total system power, cost and real estate, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII,  and a programmable Flexible I/O interface to support interfaces such as compact flash and disk drives.   Each of the 64 cores is capable of running its own operating system and is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache.

The TILE64 processor is available now in 3 different device variants based on frequency and I/O capabilities.  Production pricing for the TILE64 family starts from $435 in 10K unit quantities. Tilera's roadmap also includes plans for a 36-core and a 120-core device. 

The 64-core TILE64 chip claims 10x the performance of a dual-core Xeon and up to 40x performance of TI's DM648 DSP chip.

The device is fabricated at TSMC using standard CMOS 90nm process technology.  While not state-of-the-art, this process helps keep costs down for lower quantities.  We believe that if Tilera can reach higher volumes, they can migrate the design to smaller process nodes.

Engineers are faced with difficult choices when it comes to programming multicore chips.  They can either choose industry standard tools used for programming dual- and quad-core chips with loss of performance or they are forced into using esoteric programming models requiring rewriting all their software -- typically, a one to two year process. 

Tilera's software-based Multicore Development Environment^TM(MDE) consists of what it calls "gentle slope programming."  It supports ANSI standard C and SMP Linux so the user can compile and run an off-the-shelf application using standard tools and programming.  The existing software can run in minutes rather than waiting a year to rewrite software.  To tweak performance, MDE provides APIs to tune the core incrementally.  The MDE also supports enhanced debugging and application level profiling.  The MDE is a separate purchase in addition to unit pricing.

Multicore-based SoCs will most likely be used initially in high-end device applications like multimedia, vision analysis, and other compute intensive applications.  This will require support from RTOS and tools makers, and place greater demands on programmers to develop and de-bug multicore systems.

To date for many embedded system designers, existing software has been written with only one processor in the design and the availability of embedded software tools has been geared  to this type of development.  Multicores will demand greater complexity for developers to adapt to different programming models to distribute software functionality over multiple cores.

Engineering management are beginning to realize the large impact that software issues play in the total cost of multicore projects since existing applications may not always be easily moved over to multicores without changes.

Tilera is believed to have about 10 customers who are currently integrating the TILE64 processor into products in the advanced networking and digital multimedia space.  Several customers were named: 3Com and Top Layer in networking; Codian and GoBackTV in digital video. Products from these OEMs using the Tilera chip should appear next year.

Currently the company operates with 64 employees.  The company is headquartered in Santa Clara, Calif. with R&D operation in Westborough, Massachusetts where about 2/3 of the staff reside.  The company has a small design group in Bangalore, India which is expected to grow in the future.

Contact:

California

4677 Old Ironsides Dr., Suite 310

Santa Clara, California 95054

Web: www.tilera.com

Tel: (408) 654-7630

Fax: (408) 654-7636

Massachusetts

1900 West Park Drive, Suite 290

Westborough, Massachusetts 01581

Tel: (508) 616-9300

Fax: (508) 616-9306