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SPI Claims Highest Performance DSP
Developing applications in C for SP16HP shortens design times from months to weeks compared to the hardware-oriented methodology used in FPGA designs. The SP16HP provides a single-core programming model, eliminating the pitfalls of having to partition, synchronize and load-balance threads across multiple cores. The RapiDevTM compiler directs data movement by allowing predictable and optimal application performance and removes the need for assembly coding and manual management of caches and DMA.
Priced at $149 in quantities of 10,000 units, the SP16HP-G220 device is currently sampling with full production in the third quarter of 2007. The chip is housed in a 31x31mm flip chip ball grid array (FCBGA) package and is implemented in 130nm standard CMOS process. Contact:
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